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EMBEDDED & VLSI

Embedded Workbench

Development Tools

VLSI Design & Development Tools

IDE :- The IAR Embedded Workbench IDE is the framework where all necessary tools are

seamlessly integrated: IAR C-SPY™ debugger, state-of-the -art high-level language debugger.

IAR Embedded Workbench is available for a large number of micro-processors and micro-controllers in the 8-, 16-, and 32-bit segments, allowing you to stay within a well-known development environment also for your next project. It provides an easy-to-learn and highly efficient development environment with maximum code inheritance capabilities, comprehensive and specific target support.

 

Emulator :- The Emulation Tool Debugger is a JTAG debugger that supports all TI boards. It provides automatic flash download and takes advantage of on-chip debug facilities.

The IAR Emulator provides real-time debugging at a low cost with foll. Features

  • Execution in real time with full access to the micro-controller

  • High-speed communication through a JTAG interface

  • Zero memory footprint on target system

  • Hardware breakpoints for both code and data

 

Built-in flash downloader EEM for access also to: State storage, Sequencer and clock control.

Design Entry / Simulation :-

The ModelSim & Qsys Pro debug environment efficiently displays design data for analysis and debug of all languages. Both allow many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs with following features

  • Unified mixed language simulation engine for ease of use and performance

  • Native support of Verilog, SystemVerilog for design, and VHDL, for effective verification of sophisticated design environments

  • Advanced code coverage and analysis tools for fast time to coverage closure

  • Interactive and Post-Sim Debug available so same debug environment used for both

  • Powerful Waveform Compare for easy analysis of differences and bugs

 

Synthesis :- The Spectra-Q™ Synthesis Tool is the new synthesis engine, which integrates a new front-end language parser into the Quartus Prime software. With the new front-end parser, designers will see improved language support for all IEEE Register Transfer Level (RTL) languages. Precision RTL also includes expansive support for SystemVerilog-2005 and VHDL-2008. Support for all previously supported languages is also maintained.

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